RF identification, known by the acronym RFID (Radio Frequency IDentification), is a technology for automatic identification of objects, animals, or persons. RFID systems are based upon remote reading/writing of information contained in a tag via RFID readers.
For a better understanding of these systems, reference may be made to FIG. 1, which shows the principle diagram of a wireless data-read system using a tag. As is shown, RFID tags 1 are formed by two main components: a first antenna 2 (which is both a receiving and a transmitting antenna) and a processing circuit 3. The manufacture of an RFID tag 1 currently available on the market typically requires two distinct manufacturing steps for providing the processing circuit 3, encapsulated in a purposely provided package, and for providing the first antenna 2. Then, the first antenna 2 is mounted on the processing circuit 3, and finally these are inserted in a containment structure designed to protect the first antenna 2 and the processing circuit 3 from the outside environment. Reading of the signal sent by the first antenna 2 of the RFID tag 1 is performed via a reader 4.
Typically the RFID tags/can operate in the HF or UHF bands. The RFID tags 1 operating in the HF band (typically at the standard frequency of 13.56 MHz) communicate with the respective reader 4 in near-field-coupling conditions, i.e., principally via magnetic coupling over very small distances, in the region of approximately ten centimeters. The antenna is in this case formed by a coil of conductor material enclosing an area equal to about ten square centimeters (FIG. 2).
FIG. 2 shows in greater detail the components of the processing circuit 3 of the RFID tag 1. The processing circuit 3 comprises, cascade-connected, a resonance capacitor 5, a modulator 6, a rectifier stage 7, a booster stage 8, and a detection circuit 9. The reader 4 comprises, instead, a second antenna 10 and a control circuit 11.
FIG. 3 shows an RFID tag 1, wherein the first antenna 2 is coupled in the UHF band with the second antenna 10 of the reader 4. Usually, this type of coupling is performed in far-field conditions so as to enable the reader 4 to detect the presence of the RFID tag 1 even at a large distance. Thus, the antennas used have linear dimensions at least on the order of centimeters.
The RFID tag 1 shown in FIG. 3 moreover has an adaptation network 12, arranged on the outside of the processing circuit 3.
In the devices of FIGS. 2 and 3, the rectifier stage 7 can be of any type, for example, of the PMOS-NMOS type with cross-connected gates shown in FIG. 4, which has been implemented in the solution proposed. In detail, the rectifier stage 7 is formed by a pair of PMOS transistors M2, M4 and a pair of NMOS transistors M1, M3, with cross-connected gates, operating as switches.
A voltage generator Vs is coupled, at input terminals A, B, to the rectifier stage 7 and supplies an input square-wave signal Vs having an amplitude such as to bring the transistors M1, M2, M3, M4 into a low-resistance “on” state (sometimes called the triode region) in the high condition of the wave and to inhibit them when the voltage is zero. In detail, during the half-period when the potential of the terminal A is positive with respect to the terminal B, M1 and M2 are on, while M3 and M4 are off. In this situation, a current Ic flows from a ground node GND through M1 to the voltage generator Vs and then through M2 to a load represented in FIG. 4 by a resistor R0 and a capacitor C0.
During the half-period when the potential of the terminal A is negative with respect to the terminal B, the transistors M3 and M4 are on, while the transistors M1 and M2 are off. In this situation, the current Ic flows from ground through the transistor M3 to the voltage generator Vs and then through the transistor M4 to the load R0, C0, and then recloses to ground. Consequently, in each of the two half-periods, the current Ic that flows in the load C0, R0 always has a same direction. The current Ic charges the capacitor C0, which functions as a battery for the circuits downstream. The rectifier stage 7 generates a d.c. voltage on the capacitor C0, given by the following equation:VDC=Vs−2Von  (1)
where Vs is the amplitude of the voltage input to the rectifier stage 7, and Von is the voltage across the drain and source of the MOS transistors M1-M4 due to the resistance of their respective channels, in a triode condition. When the current Ic increases, Von increases and VDC decreases for a given Vs and a given channel resistance. The behavior of the rectifier stage 7 in the case of an input voltage Vs of a sinusoidal type is similar to the one described above, but the d.c. voltage on the load R0, C0 as well as the electrical efficiency of the rectifier circuit 7 have a lower value, since the transistors affected (M1-M2 or M3-M4) remain on in the triode condition for a time shorter than a half-period of an input square wave at the same frequency.
Given the dimensions of the transmitting antennas 2, these often cannot be integrated in the processing circuit 3 in either of the devices shown in FIGS. 2 and 3, thus leading to a high production cost, represented by the large number of manufacturing steps, and large overall dimensions of the final device.